The present invention is directed generally to semiconductor devices and methods of fabrication and more particularly to a charge storage thin film transistor array and method of fabrication.
U.S. published application Ser. No. 20020028541 which was filed as U.S. application Ser. No. 09/927,648, on Aug. 13, 2001 and which is incorporated by reference in its entirety, discloses a monolithic three dimensional array of charge storage devices. In one embodiment in this application, the charge storage devices of the array comprise both top gate staggered and inverted (i.e., bottom gate) staggered thin film transistors. Thin film transistors are called xe2x80x9cstaggeredxe2x80x9d when the gate electrode is located on the opposite side of the active layer from the source and drain electrodes. In the inverted staggered thin film transistors, the active layer and the bit lines were both made of polysilicon, and the bit lines were deposited in narrow vias in an isolation layer and then planarized to the top of the isolation layer. While deposition of a polysilicon layer to fill narrow vias is within the skill of those in the art, this deposition step is more difficult than the deposition of a polysilicon layer on a surface.
A preferred embodiment of the present invention provides a semiconductor device, comprising a word line, a charge storage region located above the word line, an active layer located above the charge storage region, a patterned etch stop layer located above a first portion of the active layer, and bit lines located over a portion of the etch stop layer and over second portions of the active layer.
Another preferred embodiment of the present invention provides a monolithic, three dimensional array of thin film transistors, comprising a first device level comprising a plurality of first inverted staggered thin film transistors, and a second device level monolithically formed over the first device level, the second device level comprising a plurality of second thin film transistors. The first inverted staggered thin film transistors comprise a first etch stop layer located over transistor channel regions.
Another preferred embodiment of the present invention provides an array of inverted staggered thin film transistors, comprising a plurality of gate lines, a planarized insulating fill layer located between the gate lines, a gate insulating layer located on the fill layer and on exposed portions of the gate lines,an active layer located on the gate insulating layer, a patterned etch stop layer located on first portions of the active layer, and a plurality of source and drain lines located on second portions of the active layer and on portions of the patterned etch stop layer.
Another preferred embodiment of the present invention provides a method of making semiconductor device, comprising forming a first gate line layer, patterning the first gate line layer to form a plurality of first gate lines, forming a first insulating fill layer over and between the first gate lines, planarizing the first fill layer with a top surface of the first gate lines, forming a first gate insulating layer over the first gate lines and the first fill layer, forming a first active layer over the first gate insulating layer, and forming a first etch stop layer over the first active layer. The method further comprises selectively patterning the first etch stop layer such that first portions of the first active layer are covered by the etch stop layer and second portions of the first active layer are exposed, forming a first source/drain line film over the first patterned etch stop layer and the exposed second portions of the first active layer, and selectively patterning the first source/drain line film to form first source and drain lines and to expose portions of the first patterned etch stop layer between the first source and drain lines.